A common problem encountered in modern Von Neuman architecture is the access of instructions and data from the same memory. In modern data processing systems, an access to memory is very time consuming as compared to instruction execution within a processing unit. The problem of time consumption due to memory access has been alleviated to some extent by the use of cache memory, a very fast memory that is connected to the data processing system to hold frequently used information. However, if the information to be accessed is not available in the cache memory, then the additional time is required to access the main memory. In a conventional pipelined data processing system, instructions are executed in sequence but in a quasi-parallel fashion. Each instruction is executed in several phases, and while one instruction phase is being executed, other phases of other instructions are also executed in parallel. As a result of the pipelined process concurrent execution of instructions is carried out in an orderly manner while maintaining the sequential relationship of the instructions. However, ordinarily when an instruction requires data from memory, the pipeline is halted while the data is fetched from the memory, thus destroying many of the advantages of the concurrent or parallel instruction prosecution in the pipeline processing. The object of the present invention is to minimize this penalty caused by the memory access.
One method used in the past to address this problem was the tagging of a register that is the target of an outstanding load operation (i.e., the register that is to receive data from memory). This technique is discussed in co-pending reissue application Ser. No. 07/285,827 filed Dec. 16, 1988, from U.S. Pat. No. 4,630,195, originally filed May 31, 1984. According to this teaching, each register of the processor include a tag storage facility. When instructions are being executed that do not require data from the tagged registers, the instruction execution is allowed to continue. However, if an instruction is being executed which depends upon data to be stored in a tagged register, and the register has not received the data as indicated by the tag, the instruction is not executed.
The object of the present invention is to provide a tagging mechanism for a data processing system that includes multiple processors where the execution of one instruction is performed in a first processor while data for the instruction is fetched by a second processor. The invention provides the sequential instruction execution capability by allowing the orderly execution of pipelined instructions while managing data accesses from memory.